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| HC55180, HC55181, HC55182, HC55183, HC55184 Data Sheet October 1998 File Number 4519.4 Extended Reach Ringing SLIC Family The RSLIC18 family of ringing subscriber line interface circuits (RSLIC) supports analog Plain Old Telephone Service (POTS) in short and medium loop length, wireless and wireline applications. Ideally suited for remote subscriber units, this family of products offers flexibility to designers with high ringing voltage and low power consumption system requirements. The RSLIC18 family operates to 100V which translates directly to the amount of ringing voltage supplied to the end subscriber. With the high operating voltage, subscriber loop lengths can be extended to 500 (i.e., 5,000 feet) and beyond. Other key features across the product family include: low power consumption, ringing using sinusoidal or trapezoidal waveforms, robust auto-detection mechanisms for when subscribers go on or off hook, and minimal external discrete application components. Integrated test access features are also offered on selected products to support loopback testing as well as line measurement tests. There are five product offerings in the RSLIC18 family: HC55180, HC55181, HC55182, HC55183 and HC55184. The architecture for this family is based on a voltage feed amplifier design using low fixed loop gains to achieve high analog performance with low susceptibility to system induced noise. Features * Battery Operation to 100V * Low Standby Power Consumption of 50mW * Peak Ringing Amplitude 95V, 5 REN * Sinusoidal or Trapezoidal Ringing Capability * Integrated CODEC Ringing Interface * Integrated MTU DC Characteristics * Low External Component Count * Pulse Metering and On Hook Transmission * Tip Open Ground Start Operation * Thermal Shutdown with Alarm Indicator * 28 Lead Surface Mount Packaging * Dielectric Isolated (DI) High Voltage Design * HC55180 - Silent Polarity Reversal - 53dB Longitudinal Balance - Loopback Test Capability * HC55181 - Integrated Battery Switch - Silent Polarity Reversal - 58/53dB Longitudinal Balance - Loopback and Test Access Capability * HC55182 - Integrated Battery Switch - 58/53dB Longitudinal Balance - Loopback and Test Access Capability * HC55183 - Integrated Battery Switch - 45dB Longitudinal Balance * HC55184 - Integrated Battery Switch - Silent Polarity Reversal - 45dB Longitudinal Balance Block Diagram POL CDC VBL VBH ILIM DC CONTROL BATTERY SWITCH RINGING PORT VRS Applications * Wireless Local Loop (WLL) VRX VTX -IN VFB TIP RING 2-WIRE PORT TRANSMIT SENSING 4-WIRE PORT * Digital Added Main Line (DAML)/Pairgain * Integrated Services Digital Network (ISDN) * Small Office Home Office (SOHO) PBX * Cable/Computer Telephony SW+ SW- TEST ACCESS DETECTOR LOGIC CONTROL LOGIC F2 F1 F0 Related Literature * AN9814, User's Guide for Development Board * AN9824, Modeling of the AC Loop * AN TBD, Interfacing to DSP CODECs RTD RD E0 DET ALM BSEL SWC 28 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. RSLIC18TM is a trademark of Intersil Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 HC55180, HC55181, HC55182, HC55183, HC55184 Ordering Information (PLCC Package Only) BAT SW POL REV FULL TEST LOOP BACK ONLY TEMP. RANGE oC -40 to 85 -40 to 85 PACKAGE NO. N28.45 N28.45 N28.45 N28.45 N28.45 N28.45 N28.45 N28.45 N28.45 N28.45 N28.45 N28.45 PART NUMBER HC55180CIM HC55180DIM HC55181AIM HC55181BIM HC55181CIM HC55181DIM HC55182AIM HC55182BIM HC55182CIM HC55182DIM HC55183ECM HC55184ECM HC5518XEVAL1 100V 85V LB = 53dB LB = 58dB PACKAGE 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC * * * * * * * * * * 75V 75V * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 45dB 45dB -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 Evaluation board platform, including CODEC. Device Operating Modes OPERATING MODE Low Power Standby F2 0 F1 0 F0 0 E0 = 1 E0 = 0 SHD GKD DESCRIPTION MTU compliant standby mode with active loop detector. Forward battery loop feed. This is a reserved internal test mode. Reverse battery loop feed. Balanced ringing mode supporting both sinusoidal, trapezoidal and ringing waveforms with DC offset. Internal device test mode. HC55180 HC55181 HC55182 HC55183 HC55184 * * * * * Forward Active Unused 0 0 0 1 1 0 SHD n/a GKD n/a * * * * * Reverse Active Ringing 0 1 1 0 1 0 SHD RTD GKD RTD * * * * * * * * Forward Loop Back Tip Open 1 0 1 SHD GKD * * * * * * 1 1 0 SHD GKD Tip amplifier disabled and ring amplifier enabled. Intended for PBX type applications. Device shutdown. Power Denial 1 1 1 n/a n/a * * * * * 29 HC55180, HC55181, HC55182, HC55183, HC55184 Pinouts HC55180 (PLCC) TOP VIEW BGND RING VBH VBL TIP ILIM 25 RTD 24 CDC 23 VCC 22 -IN 21 VFB 20 VTX 19 VRX 12 DET 13 ALM 14 15 AGND NC 16 NC 17 POL 18 VRS RD 4 NC NC NC F2 F1 F0 E0 5 6 7 8 9 10 11 3 2 1 28 27 26 HC55181 (PLCC) TOP VIEW BGND RING ILIM VBH VBH VBL VBL TIP RD HC55182 (PLCC) TOP VIEW BGND RING TIP ILIM 25 RTD 24 CDC 23 VCC 22 -IN 21 VFB 20 VTX 19 VRX 12 DET 13 ALM 14 15 BSEL AGND 16 NC 17 NC ILIM 25 RTD 24 CDC 23 VCC 22 -IN 21 VFB 20 VTX 19 VRX 12 DET 13 ALM 14 15 BSEL AGND 16 NC 17 POL 18 VRS 18 VRS RD 4 SW+ SWSWC F2 F1 F0 E0 5 6 7 8 9 10 11 12 DET 3 2 1 28 27 26 25 RTD 24 CDC 23 VCC 22 -IN 21 VFB 20 VTX 19 VRX SW+ SWSWC F2 F1 F0 E0 5 6 7 8 9 10 11 4 3 2 1 28 27 26 13 ALM 14 15 BSEL AGND 16 NC 17 POL 18 VRS HC55183 (PLCC) TOP VIEW BGND RING VBH ILIM VBH VBL VBL TIP RD HC55184 (PLCC) TOP VIEW BGND RING TIP RD 4 NC NC NC F2 F1 F0 E0 5 6 7 8 9 10 11 12 DET 3 2 1 28 27 26 25 RTD 24 CDC 23 VCC 22 -IN 21 VFB 20 VTX 19 VRX NC NC NC F2 F1 F0 E0 5 6 7 8 9 10 11 4 3 2 1 28 27 26 13 ALM 14 15 BSEL AGND 16 NC 17 NC 18 VRS 30 HC55180, HC55181, HC55182, HC55183, HC55184 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (PLCC - Lead Tips Only) Maximum Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V VCC - VBAT (180, 181, 182) . . . . . . . . . . . . . . . . . . . . . . . . . 110V VCC - VBAT (183, 184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85V Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V Operating Conditions Temperature Range Industrial (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Commercial (C suffix). . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Positive Power Supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Negative Power Supply (VBH, VBL) (180, 181, 182) . -16V to -100V Negative Power Supply (VBH, VBL) (183, 184) . . . . . . -24V to -75V Uncommitted Switch (loop back or relay driver). . . . . . +5V to -100V Die Characteristics Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0. These parameters apply generically to each product offering. TEST CONDITIONS MIN TYP MAX UNITS PARAMETER RINGING PARAMETERS (Note 2) VRS Input Impedance (Note 3) Differential Ringing Gain 4-Wire to 2-Wire Ringing Off Isolation 2-Wire to 4-Wire Transmit Isolation AC TRANSMISSION PARAMETERS (Notes 5, 6) Receive Input Impedance (Note 3) Transmit Output Impedance (Note 3) 4-Wire Port Overload Level 2-Wire Port Overload Level 2-Wire Return Loss THD = 1% THD = 1% 480 VRS to 2-wire, RLOAD = (Note 4) Active mode, referenced to VRS input. Ringing mode referenced to the differential ringing amplitude. 78 - 80 60 60 82 - k V/V dB dB 160 3.1 3.1 30 35 20 10 -0.20 -6.22 -6.22 C-Message Psophometric - 3.5 3.5 45 45 0.0 -6.02 -6.02 16 -73.5 10 -79.5 1 +0.30 -5.82 -5.82 19 -71 13 -77 k VPK VPK dB dB mARMS mARMS dB dB dB dBrnC dBmp dBrnC dBmp 300Hz f < 1kHz 1kHz f 3.4kHz Longitudinal Current Capability (Per Wire) (Note 3) Test for False Detect Test for False Detect, Low Power Standby 4-Wire to 2-Wire Insertion Loss 2-Wire to 4-Wire Insertion Loss 4-Wire to 4-Wire Insertion Loss Idle Channel Noise 2-Wire Idle Channel Noise 4-Wire C-Message Psophometric DC PARAMETERS (Note 6) Loop Current Limit Programming Range (Note 5) Loop Current During Low Power Standby Max Low Battery = -52V Forward polarity only. 15 18 45 26 mA mA 31 HC55180, HC55181, HC55182, HC55183, HC55184 Electrical Specifications Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0. These parameters apply generically to each product offering. (Continued) TEST CONDITIONS MIN TYP MAX UNITS PARAMETER LOOP DETECTORS AND SUPERVISORY FUNCTIONS Switch Hook Programming Range Switch Hook Programming Accuracy Dial Pulse Distortion Ring Trip Comparator Threshold Ring Trip Programming Current Accuracy Ground Key Threshold Thermal Alarm Output LOGIC INPUTS (F0, F1, F2, E0, SWC) Input Low Voltage Input High Voltage Input Low Current Input High Current LOGIC OUTPUTS (DET, ALM) Output Low Voltage Output High Voltage POWER SUPPLY REJECTION RATIO VCC to 2-Wire f = 300Hz f = 1kHz f = 3.4kHz VCC to 4-Wire f = 300Hz f = 1kHz f = 3.4kHz VBL to 2-Wire VBL to 4-Wire VBH to 2-Wire VBH to 4-Wire IOL = 5mA IOH = 100 A VIL = 0.4V VIH = 2.4V 5 Assumes 1% external programming resistor 2.3 10 IC junction temperature - 2 2.6 12 175 15 10 1 2.9 10 13.5 - mA % % V % mA oC 2.0 -20 - - 0.8 5 V V A A 2.4 - 0.4 - V V - 40 35 28 45 43 33 30 35 33 40 45 - dB dB dB dB dB dB dB dB dB dB dB 300Hz f 3.4kHz 300Hz f 3.4kHz 300Hz f 3.4kHz 300Hz f 1kHz 1kHz < f 3.4kHz NOTES: 2. These parameters are specified at high battery operation. For the HC55180 the external supply is set to high battery voltage, for the HC55181, HC55182, HC55183 and HC55184, BSEL = 1. 3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 4. Differential Ringing Gain is measured with VRS = 0.795 VRMS for -100V devices, VRS = 0.663 VRMS for -85V devices and VRS = 0.575 VRMS for -75V devices. 5. These parameters are specified at low battery operation. For the HC55180, the external supply is set to low battery voltage, for the HC55181, HC55182, HC55183 and HC55184, BSEL = 0. 6. Forward Active and Reverse Active performance is guaranteed for the HC55180, HC55181 and HC55184 devices only. The HC55182 and HC55183 are specified for Forward Active operation only. 32 Electrical Specifications Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. HC55180 (Note 7) HC55181, HC55182 TYP 80 95 80 95 2.5 2.0 2.5 2.0 59 64 0.025 0.050 0.100 MAX TEST CONDITIONS THD 0.5% VBH = -85V THD 0.5% VBH = -100V THD 2.5% VBH = -85V THD 2.0% VBH = -100V VBH = -85V, RL = VBH = -100V, RL = VBH = -85V, RL = VBH = -100V, RL = Grade A, B Grade C, D Grade A, B Grade C, D +3 to -40dBm, 1kHz -40 to -50dBm, 1kHz -50 to -55dBm, 1kHz MIN 80 95 80 95 58 53 TYP 62 59 67 64 0.025 0.050 0.100 MAX 2.5 2.0 2.5 2.0 HC55183, HC55184 TEST CONDITIONS THD 0.5% VBH = -75V (Note 9) THD 3.0% VBH = -75V (Note 9) VBH = -75V, RL = (Note 9) VBH = -75V, RL = (Note 9) Grade E (Note 11) Grade E (Note 11) +3 to -40dBm, 1kHz -40 to -50dBm, 1kHz -50 to -55dBm, 1kHz MIN 70 70 45 TYP 53 58 0.025 0.050 0.100 MAX 3 3 UNITS VPEAK VPEAK TEST CONDITIONS MIN - PARAMETER Ringing Voltage Open Circuit (Note 8) RINGING PARAMETERS (Note 2) THD 0.5% VB = -85V THD 0.5% VB = -100V THD 2.5% VB = -85V THD 2.0% VB = -100V VB = -85V, RL = VB = -100V, RL = Ring Centering Voltage VB = -85V, RL = VB = -100V, RL = AC TRANSMISSION PARAMETERS (Notes 5, 6) 2-Wire Longitudinal Balance (Notes 12, 13) 4-Wire Longitudinal Balance (Note 11) Grade C, D (Note 11) Grade C, D 2-Wire to 4-Wire Level Linearity +3 to -40dBm, 1kHz 4-Wire to 2-Wire Level -40 to -50dBm, 1kHz Linearity -50 to -55dBm, 1kHz Referenced to -10dBm DC PARAMETERS Loop Current Accuracy (Notes 5, 6) Open Circuit Voltage (|Tip - Ring|, Note 6) IL = 25mA VB = -16V VB = -24V VB = -85V VB = -100V Low Power Standby Open Circuit Voltage (Tip - Ring, Note 2) TEST ACCESS FUNCTIONS Switch On Voltage Loopback Max Battery (Note 14) 52 IOL = 45mA 0.30 0.60 52 (Note 14) (Note 15) 52 V V VB = -48V VB = -85V VB = -100V 14 43 46 46 7 7.5 15.5 50 50 45 49 49 17 47 52 52 IL = 25mA VBL = -16V VBL = -24V BSEL = 1, VBH = -85V BSEL = 1, VBH = -100V VBH = -48V VBH = -85V VBH = -100V 6.5 14 43 46 46 7.5 15.5 50 50 45 49 49 7 9.5 17 47 52 52 IL = 25mA VBL = -16V VBL = -24V BSEL = 1, VBH = -75V (Note 9) VBH = -48V VBH = -75V (Note 9) 14 43 46 7.5 15.5 50 45 49 10 17 47 52 % V V V V V V V dB dB dB dB dB dB dB 33 HC55180, HC55181, HC55182, HC55183, HC55184 Ringing Voltage Load = 1.3K (Notes 8, 10) Tip Centering Voltage VPEAK VPEAK V V V V Electrical Specifications Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. (Continued) HC55180 (Note 7) HC55181, HC55182 TYP 3.7 0.375 4.0 1.0 5.5 3.2 7.5 2.3 8.5 19 3.0 0.2 44 52 59 190 220 290 MAX 5.0 5.0 2.5 7.0 4.5 11 5.0 10.0 23.5 5.5 1.0 5.0 0.5 60 TEST CONDITIONS ICC ICC IBL ICC IBL IBH , VBH = -100V, -85V ICC IBL IBH , VBH = -100V, -85V ICC IBL ICC IBL ICC IBL VBL = -24V VBH = -85V VBH = -100V VBH = -85V VBH = -100V VBL = -24V MIN 2.0 2.5 3.5 4.5 0.5 TYP 3.7 0.375 4.0 1.0 5.5 1.3 1.7 7.5 0.4 1.3 8.5 19 3.0 0.2 44 52 59 190 220 290 MAX 5.0 5.0 2.5 7.0 2.0 2.5 11 7.5 2.5 10.0 23.5 5.5 1.0 4.5 0.5 60 65 75 275 300 310 ICC IBL VBL = -24V VBH = -75V (Note 9) VBH = -75V (Note 9) VBL = -24V 280 310 mW 170 250 mW (Note 16) HC55183, HC55184 TEST CONDITIONS ICC ICC IBL ICC IBL IBH, VBH = -75V ICC IBL IBH, VBH = -75V (Note 15) MIN 2.0 2.0 TYP 3.7 0.375 4.0 1.0 5.5 1.3 1.4 7.5 0.4 1.3 3.0 0.2 44 46 MAX 6.0 6.0 2.5 8.0 2.5 3.0 11 1.5 2.5 5.0 0.5 60 65 UNITS mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW mW TEST CONDITIONS MIN 2.0 2.5 3.5 4.5 0.5 - PARAMETER Low Power Standby (Note 2) Forward or Reverse (Note 5) Forward (Note 2) SUPPLY CURRENTS (Supply currents not listed are considered negligible and do not contribute significantly to total power dissipation. All measurements made under open circuit load conditions.) ICC IB , VB = -100V, -85V ICC IB , VB = -24V ICC (Note 7) IB , VB = -100V, -85V Ringing (Note 2) ICC (Note 7) IB , VB = -100V, -85V Forward Loopback (Note 5) Tip Open (Note 5) Power Denial (Note 5) ICC IB , VB = -24V ICC IB , VB = -24V ICC IB , VB = -24V VB = -24V VB = -85V VB = -100V VB = -85V VB = -100V VB = -24V 0.600 IBH , VBH = -100V, -85V 0.600 IBH, VBH = -75V 34 HC55180, HC55181, HC55182, HC55183, HC55184 ON HOOK POWER DISSIPATION (Note 17) Forward or Reverse (Notes 5, 6) Low Power Standby (Note 2) Ringing (Note 2) OFF HOOK POWER DISSIPATION (Notes 5, 17) Forward or Reverse NOTES: 7. The HC55180 does not provide battery switch operation. Therefore all battery voltage references will be made to VB. VB is the voltage applied to the common connection of the device VBL and VBH pins. See the HC55180 Basic Application Circuit. 8. Ringing Voltage is measured with VRS = 0.839 VRMS for -100V devices, VRS = 0.707 VRMS for -85V devices and VRS = 0.619 VRMS for -75V devices. 9. The HC55183 and HC55184 devices are specified with a single high battery voltage grade. 10. The device represents a low output impedance during ringing. Therefore the voltage across the ringing load is determined by the voltage divider formed by the protection resistance, loop resistance and ringing load impedance. 11. The HC55180, HC55183 and HC55184 are specified with a single longitudinal balance grade. 12. Longitudinal Balance is tested per IEEE455-1985, with 368 per Tip and Ring Terminal. 13. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical characterization. 14. The HC55180, HC55183 and HC55184 do not support uncommitted switch operation. 15. The HC55183 and HC55184 do not support the Forward Loopback operating mode. 16. The HC55183 and HC55184 do not support the Tip Open operating mode. 17. The power dissipation numbers are actual device measurements and will be less than worse case calculations based on data sheet supply current limits. HC55180, HC55181, HC55182, HC55183, HC55184 Design Equations Loop Supervision Thresholds SWITCH HOOK DETECT The switch hook detect threshold is set by a single external resistor, RSH . Equation 1 is used to calculate the value of RSH. R SH = 600 I SH (EQ. 1) 4-WIRE TO 2-WIRE GAIN The 4-wire to 2-wire gain is defined as the receive gain. It is a function of the terminating impedance, synthesized impedance and protection resistors. Equation 6 calculates the receive gain, G42. ZL G 42 = - 2 ----------------------------------------- Z O + 2R P + Z L (EQ. 6) The term ISH is the desired DC loop current threshold. The loop current threshold programming range is from 5mA to 15mA. GROUND KEY DETECT The ground key detector senses a DC current imbalance between the Tip and Ring terminals when the ring terminal is connected to ground. The ground key detect threshold is not externally programmable and is internally fixed to 12mA regardless of the switch hook threshold. RING TRIP DETECT The ring trip detect threshold is set by a single external resistor, RRT. IRT should be set between the peak ringing current and the peak off hook current while still ringing. R RT = 1800 I RT (EQ. 2) When the device source impedance and protection resistors equals the terminating impedance, the receive gain equals unity. 2-WIRE TO 4-WIRE GAIN The 2-wire to 4-wire gain (G24) is the gain from tip and ring to the VTX output. The transmit gain is calculated in Equation 7. ZO G 24 = - ----------------------------------------- Z O + 2R P + Z L (EQ. 7) When the protection resistors are set to zero, the transmit gain is -6dB. TRANSHYBRID GAIN The transhybrid gain is defined as the 4-wire to 4-wire gain (G44). ZO G 44 = - -------------------------------------- Z O + 2R P + Z L (EQ. 8) The capacitor CRT, in parallel with RRT, will set the ring trip response time. Loop Current Limit The loop current limit of the device is programmed by the external resistor RIL. The value of RIL can be calculated using Equation 3. 1760 R IL = -----------I LIM (EQ. 3) When the protection resistors are set to zero, the transhybrid gain is -6dB. COMPLEX IMPEDANCE SYNTHESIS Substituting the impedance programming resistor, RS, with a complex programming network provides complex impedance synthesis. 2-WIRE NETWORK C2 R1 R2 PROGRAMMING NETWORK CP RS RP The term ILIM is the desired loop current limit. The loop current limit programming range is from 15mA to 45mA. Impedance Matching The impedance of the device is programmed with the external component RS . RS is the gain setting resistor for the feedback amplifier that provides impedance matching. If complex impedance matching is required, then a complex network can be substituted for RS . RESISTIVE IMPEDANCE SYNTHESIS The source impedance of the device, ZO , can be calculated in Equation 4. R S = 400 ( Z O ) (EQ. 4) FIGURE 1. COMPLEX PROGRAMMING NETWORK The reference designators in the programming network match the evaluation board. The component RS has a different design equation than the RS used for resistive impedance synthesis. The design equations for each component are provided below. R S = 400 x ( R 1 - 2 ( R P ) ) R P = 400 x R 2 C P = C 2 400 (EQ. 9) (EQ. 10) (EQ. 11) The required impedance is defined by the terminating impedance and protection resistors as shown in Equation 5. Z O = Z L - 2R P (EQ. 5) 35 HC55180, HC55181, HC55182, HC55183, HC55184 Low Power Standby Overview The low power standby mode (LPS, 000) should be used during idle line conditions. The device is designed to operate from the high battery during this mode. Most of the internal circuitry is powered down, resulting in low power dissipation. If the 2-wire (tip/ring) DC voltage requirements are not critical during idle line conditions, the device may be operated from the low battery. Operation from the low battery will decrease the standby power dissipation. TABLE 1. DEVICE INTERFACES DURING LPS INTERFACE Receive Ringing Transmit 2-Wire Loop Detect x x ON OFF x x x Amplifiers disabled. Switch hook or ground key. NOTES AC transmission, impedance matching and ringing are disabled during this mode. Ring terminal will be clamped by the internal reference. The same Ring relationships apply when operating from the low battery voltage. For high battery voltages (VBH) less than or equal to the internal MTU reference threshold: V RING = V BH + 4 (EQ. 12) Loop Current During LPS, the device will provide current to a load. The current path is through resistors and switches, and will be function of the off hook loop resistance (RLOOP). This includes the off hook phone resistance and copper loop resistance. The current available during LPS is determined by Equation 13. I LOOP = ( - 1 - ( - 49 ) ) ( 600 + 600 + R LOOP ) (EQ. 13) Internal current limiting of the standby switches will limit the maximum current to 20mA. Another loop current related parameter is longitudinal current capability. The longitudinal current capability is reduced to 10mARMS per pin. The reduction in longitudinal current capability is a result of turning off the Tip and Ring amplifiers. 2-Wire Interface During LPS, the 2-wire interface is maintained with internal switches and voltage references. The Tip and Ring amplifiers are turned off to conserve power. The device will provide MTU compliance, loop current and loop supervision. Figure 2 represents the internal circuitry providing the 2-wire interface during low power standby. GND 600 TIP AMP TIP On Hook Power Dissipation The on hook power dissipation of the device during LPS is determined by the operating voltages and quiescent currents and is calculated using Equation 14. P LPS = V BH x I BHQ + V BL x I BLQ + V CC x I CCQ (EQ. 14) RING RING AMP 600 MTU REF The quiescent current terms are specified in the electrical tables for each operating mode. Load power dissipation is not a factor since this is an on hook mode. Some applications may specify a standby current. The standby current may be a charging current required for modern telephone electronics. Standby Current Power dissipation Any standby line current, ISLC , introduces an additional power dissipation term PSLC . Equation 15 illustrates the power contribution is zero when the standby line current is zero. P SLC = I SLC x ( V BH - 49 + 1 + I SLC x1200 ) (EQ. 15) FIGURE 2. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM MTU Compliance Maintenance Termination Unit or MTU compliance places DC voltage requirements on the 2-wire terminals during idle line conditions. The minimum idle voltage is 42.75V. The high side of the MTU range is 56V. The voltage is expressed as the difference between Tip and Ring. The Tip voltage is held near ground through a 600 resistor and switch. The Ring voltage is limited to a maximum of -49V (by MTU REF) when operating from either the high or low battery. A switch and 600 resistor connect the MTU reference to the Ring terminal. When the high battery voltage exceeds the MTU reference of -49V (typically), the If the battery voltage is less than -49V (the MTU clamp is off), the standby line current power contribution reduces to Equation 16. P SLC = I SLC x ( V BH + 1 + I SLC x1200 ) (EQ. 16) Most applications do not specify charging current requirements during standby. When specified, the typical charging current may be as high as 5mA. 36 HC55180, HC55181, HC55182, HC55183, HC55184 Forward Active Overview The forward active mode (FA, 001) is the primary AC transmission mode of the device. On hook transmission, DC loop feed and voice transmission are supported during forward active. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The device may be operated from either high or low battery for onhook transmission and low battery for loop feed. Most applications will operate the device from low battery while off hook. The DC feed characteristic of the device will drive Tip and Ring towards half battery to regulate the DC loop current. For light loads, Tip will be near -4V and Ring will be near VVBL + 4V. The following diagram shows the DC feed characteristic. VTR(OC) VTR , DC (V) m = (VTR/IL) = 10k On-Hook Transmission The primary purpose of on hook transmission will be to support caller ID and other advanced signalling features. The transmission over load level while on hook is 3.5VPEAK . When operating from the high battery, the DC voltages at Tip and Ring are MTU compliant. The typical Tip voltage is -4V and the Ring voltage is a function of the battery voltage for battery voltages less than -60V as shown in Equation 17. V RING = V BH + 4 (EQ. 17) ILOOP (mA) ILIM FIGURE 4. DC FEED CHARACTERISTIC The point on the y-axis labeled VTR(OC) is the open circuit Tip to Ring voltage and is defined by the feed battery voltage. V TR ( OC ) = V BL - 8 (EQ. 18) Loop supervision is provided by the switch hook detector at the DET output. When DET goes low, the low battery should be selected for DC loop feed and voice transmission. Feed Architecture The design implements a voltage feed current sense architecture. The device controls the voltage across Tip and Ring based on the sensing of load current. Resistors are placed in series with Tip and Ring outputs to provide the current sensing. The diagram below illustrates the concept. RB RCS VOUT RL RA VIN The curve of Figure 5 determines the actual loop current for a given set of loop conditions. The loop conditions are determined by the low battery voltage and the DC loop impedance. The DC loop impedance is the sum of the protection resistance, copper resistance (ohms/foot) and the telephone off hook DC resistance. ISC ILIM ILOOP (mA) IA IB 2RP RLOOP () RKNEE + RC - FIGURE 5. ILOOP VERSUS RLOOP LOAD CHARACTERISTIC - + KS The slope of the feed characteristic and the battery voltage define the maximum loop current on the shortest possible loop as the short circuit current ISC. V TR ( OC ) - 2R P I LIM I SC = I LIM + ----------------------------------------------------10e3 (EQ. 19) FIGURE 3. VOLTAGE FEED CURRENT SENSE DIAGRAM By monitoring the current at the amplifier output, a negative feedback mechanism sets the output voltage for a defined load. The amplifier gains are set by resistor ratios (RA , RB , RC) providing all the performance benefits of matched resistors. The internal sense resistor, RCS , is much smaller than the gain resistors and is typically 20 for this device. The feedback mechanism, KS , represents the amplifier configuration providing the negative feedback. The term ILIM is the programmed current limit, 1760/RIL. The line segment IA represents the constant current region of the loop current limit function. V TR ( OC ) - R LOOP I LIM I A = I LIM + -------------------------------------------------------------10e3 (EQ. 20) The maximum loop impedance for a programmed loop current is defined as RKNEE . V TR ( OC ) R KNEE = ----------------------I LIM (EQ. 21) DC Loop Feed The feedback mechanism for monitoring the DC portion of the loop current is the loop detector. A low pass filter is used in the feedback to block voice band signals from interfering with the loop current limit function. The pole of the low pass filter is set by the external capacitor CDC . The value of the external capacitor should be 4.7F. When RKNEE is exceeded, the device will transition from constant current feed to constant voltage, resistive feed. The line segment IB represents the resistive feed portion of the load characteristic. V TR ( OC ) I B = ----------------------R LOOP (EQ. 22) 37 HC55180, HC55181, HC55182, HC55183, HC55184 Voice Transmission The feedback mechanism for monitoring the AC portion of the loop current consists of two amplifiers, the sense amplifier (SA) and the transmit amplifier (TA). The AC feedback signal is used for impedance synthesis. A detailed model of the AC feed back loop is provided below. R 20 TIP 20 RING R VRX + 1:1 -IN HC5518x CODEC R R VRX R 1:1 VTX TA + RS RB RA RF RX OUT - + TX IN +2.4V - - FIGURE 7. TRANSHYBRID BALANCE INTERFACE + - VTX TA + RS -IN 8K VSA CFB VFB R 3R 3R 3R 3R 0.75R The resistor ratio, RF /RB , provides the final adjustment for the transmit gain, GTX . The transmit gain is calculated using Equation 25. R F G TX = - G 24 ------- R B (EQ. 25) - - + R/2 Most applications set RF = RB , hence the device 2-wire to 4-wire equals the transmit gain. Typically RB is greater than 20k to prevent loading of the device transmit output. The resistor ratio, RF /RA , is determined by the transhybrid gain of the device, G44 . RF is previously defined by the transmit gain requirement and RA is calculated using Equation 26. RB R A = --------G 44 (EQ. 26) FIGURE 6. AC SIGNAL TRANSMISSION MODEL The gain of the transmit amplifier, set by RS , determines the programmed impedance of the device. The capacitor CFB blocks the DC component of the loop current. The ground symbols in the model represent AC grounds, not actual DC potentials. The sense amp output voltage, VSA , as a function of Tip and Ring voltage and load is calculated using Equation 23. 10 V SA = - ( V T - V R ) -----ZL (EQ. 23) Power Dissipation The power dissipated by the device during on hook transmission is strictly a function of the quiescent currents for each supply voltage during Forward Active operation. + V BL x I BLQ + V CC x I CCQ P FAQ = V BH x I BHQ (EQ. 27) The transmit amplifier provides the programmable gain required for impedance synthesis. In addition, the output of this amplifier interfaces to the CODEC transmit input. The output voltage is calculated using Equation 24. RS V VTX = - V SA ---------- 8e3 (EQ. 24) Once the impedance matching components have been selected using the design equations, the above equations provide additional insight as to the expected AC node voltages for a specific Tip and Ring load. Transhybrid Balance The final step in completing the impedance synthesis design is calculating the necessary gains for transhybrid balance. The AC feed back loop produces an echo at the VTX output of the signal injected at VRX . The echo must be cancelled to maintain voice quality. Most applications will use a summing amplifier in the CODEC front end as shown below to cancel the echo signal. Off hook power dissipation is increased above the quiescent power dissipation by the DC load. If the loop length is less than or equal to RKNEE , the device is providing constant current, IA , and the power dissipation is calculated using Equation 28. P FA ( IA ) = P FA ( Q ) + ( V BL xI A ) - ( R LOOP xI 2 A ) (EQ. 28) If the loop length is greater than RKNEE , the device is operating in the constant voltage, resistive feed region. The power dissipated in this region is calculated using Equation 29. P FA ( IB ) = P FA ( Q ) + ( V BL xI B ) - ( R LOOP xI 2 B ) (EQ. 29) Since the current relationships are different for constant current versus constant voltage, the region of device operation is critical to valid power dissipation calculations. 38 HC55180, HC55181, HC55182, HC55183, HC55184 Reverse Active Overview The reverse active mode (RA, 011) provides the same functionality as the forward active mode. On hook transmission, DC loop feed and voice transmission are supported. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The device may be operated from either high or low battery. During reverse active the Tip and Ring DC voltage characteristics exchange roles. That is, Ring is typically 4V below ground and Tip is typically 4V more positive than battery. Otherwise, all feed and voice transmission characteristics are identical to forward active. Ringing Overview The ringing mode (RNG, 100) provides linear amplification to support a variety of ringing waveforms. A programmable ring trip function provides loop supervision and auto disconnect upon ring trip. The device is designed to operate from the high battery during this mode. Architecture The device provides linear amplification to the signal applied to the ringing input, VRS . The differential ringing gain of the device is 80V/V. The circuit model for the ringing path is shown in the following figure. R R/8 20 TIP + 5:1 20 RING + + VBH 2 800K Silent Polarity Reversal Changing from forward active to reverse active or vice versa is referred to as polarity reversal. Many applications require slew rate control of the polarity reversal event. Requirements range from minimizing cross talk to protocol signalling. The device uses an external low voltage capacitor, CPOL , to set the reversal time. Once programmed, the reversal time will remain nearly constant over various load conditions. In addition, the reversal timing capacitor is isolated from the AC loop, therefore loop stability is not impacted. The internal circuitry used to set the polarity reversal time is shown below. I1 POL - + - VRS - R FIGURE 9. LINEAR RINGING MODEL The voltage gain from the VRS input to the Tip output is 40V/V. The resistor ratio provides a gain of 8 and the current mirror provides a gain of 5. The voltage gain from the VRS input to the Ring output is -40V/V. The equations for the Tip and Ring outputs during ringing are provided below. V BH V T = ----------- + ( 40 x VRS ) 2 V BH V R = ----------- - ( 40 x VRS ) 2 (EQ. 31) (EQ. 32) 75k I2 CPOL FIGURE 8. REVERSAL TIMING CONTROL During forward active, the current from source I1 charges the external timing capacitor CPOL and the switch is open. The internal resistor provides a clamping function for voltages on the POL node. During reverse active, the switch closes and I2 (roughly twice I1) pulls current from I1 and the timing capacitor. The current at the POL node provides the drive to a differential pair which controls the reversal time of the Tip and Ring DC voltages. time C POL = ---------------75000 (EQ. 30) When the input signal at VRS is zero, the Tip and Ring amplifier outputs are centered at half battery. The device provides auto centering for easy implementation of sinusoidal ringing waveforms. Both AC and DC control of the Tip and Ring outputs is available during ringing. This feature allows for DC offsets as part of the ringing waveform. Ringing Input The ringing input, VRS , is a high impedance input. The high impedance allows the use of low value capacitors for AC coupling the ring signal. The VRS input is enabled only during the ringing mode, therefore a free running oscillator may be connected to VRS at all times. When operating from a battery of -100V, each amplifier, Tip and Ring, will swing a maximum of 95VP-P. Hence, the maximum signal swing at VRS to achieve full scale ringing is approximately 2.4VP-P. The low signal levels are compatible with the output voltage range of the CODEC. The digital nature of the CODEC ideally suits it for the function of programmable ringing generator. See Applications. Where time is the required reversal time. Polarized capacitors may be used for CPOL . The low voltage at the POL pin and minimal voltage excursion 0.75V, are well suited to polarized capacitors. Power Dissipation The power dissipation equations for forward active operation also apply to the reverse active mode. 39 HC55180, HC55181, HC55182, HC55183, HC55184 Logic Control Ringing patterns consist of silent intervals. The ringing to silent pattern is called the ringing cadence. During the silent portion of ringing, the device can be programmed to any other operating mode. The most likely candidates are low power standby or forward active. Depending on system requirements, the low or high battery may be selected. Loop supervision is provided with the ring trip detector. The ring trip detector senses the change in loop current when the phone is taken off hook. The loop detector full wave rectifies the ringing current, which is then filtered with external components RRT and CRT. The resistor RRT sets the trip threshold and the capacitor CRT sets the trip response time. Most applications will require a trip response time less than 150ms. Three very distinct actions occur when the devices detects a ring trip. First, the DET output is latched low. The latching mechanism eliminates the need for software filtering of the detector output. The latch is cleared when the operating mode is changed externally. Second, the VRS input is disabled, removing the ring signal from the line. Third, the device is internally forced to the forward active mode. Forward Loop Back Overview The forward loop back mode (FLB, 101) provides test capability for the device. An internal signal path is enabled allowing for both DC and AC verification. The internal 600 terminating resistor has a tolerance of 20%. The device is intended to operate from only the low battery during this mode. Architecture When the forward loop back mode is initiated internal switches connect a 600 load across the outputs of the Tip and Ring amplifiers. TIP TIP AMP 600 RING AMP RING FIGURE 10. FORWARD LOOP BACK INTERNAL TERMINATION Power Dissipation The power dissipation during ringing is dictated by the load driving requirements and the ringing waveform. The key to valid power calculations is the correct definition of average and RMS currents. The average current defines the high battery supply current. The RMS current defines the load current. The cadence provides a time averaging reduction in the peak power. The total power dissipation consists of ringing power, Pr , and the silent interval power, Ps . tr ts P RNG = P r x ------------- + P s x ------------t +t t +t r s r DC Verification When the internal signal path is provided, DC current will flow from Tip to Ring. The DC current will force DET low, indicating the presence of loop current. In addition, the ALM output will also go low. This does not indicate a thermal alarm condition. Rather, proper logic operation is verified in the event of a thermal shutdown. In addition to verifying device functionality, toggling the logic outputs verifies the interface to the system controller. (EQ. 33) s AC Verification The entire AC loop of the device is active during the forward loop back mode. Therefore a 4-wire to 4-wire level test capability is provided. Depending on the transhybrid balance implementation, test coverage is provided by a one or two step process. System architectures which cannot disable the transhybrid function would require a two step process. The first step would be to send a test tone to the device while on hook and not in forward loop back mode. The return signal would be the test level times the gain RF /RA of the transhybrid amplifier. Since the device would not be terminated, cancellation would not occur. The second step would be to program the device to FLB and resend the test tone. The return signal would be much lower in amplitude than the first step, indicating the device was active and the internal termination attenuated the return signal. System architectures which disable the transhybrid function would achieve test coverage with a signal step. Once the transhybrid function is disable, program the device for FLB and send the test tone. The return signal level is determined by the 4-wire to 4-wire gain of the device. The terms tR and tS represent the cadence. The ringing interval is tR and the silent interval is tS . The typical cadence ratio tR :tS is 1:2. The quiescent power of the device in the ringing mode is defined in Equation 34. P r ( Q ) = V BH x I BHQ + V BL x I BLQ + V CC x I CCQ (EQ. 34) The total power during the ringing interval is the sum of the quiescent power and loading power: V RMS P r = P r ( Q ) + V BH x I AVG - ----------------------------------------Z +R REN 2 (EQ. 35) LOOP For sinusoidal waveforms, the average current, IAVG , is defined in Equation 36. V RMS x 2 2 I AVG = -- ---------------------------------------- Z +R REN (EQ. 36) LOOP The silent interval power dissipation will be determined by the quiescent power of the selected operating mode. 40 HC55180, HC55181, HC55182, HC55183, HC55184 Tip Open Overview The tip open mode (110) is intended for compatibility for PBX type interfaces. Used during idle line conditions, the device does not provide transmission. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The ground key detector will be used in most applications. The device may be operated from either high or low battery. Battery Switching Overview The integrated battery switch selects between the high battery and low battery. The battery switch is controlled with the logic input BSEL. When BSEL is a logic high, the high battery is selected and when a logic low, the low battery is selected. All operating modes of the device will operate from high or low battery except forward loop back. Functionality The logic control is independent of the operating mode decode. Independent logic control provides the most flexibility and will support all application configurations. When changing device operating states, battery switching should occur simultaneously with or prior to changing the operating mode. In most cases, this will minimize overall power dissipation and prevent glitches on the DET output. The only external component required to support the battery switch is a diode in series with the VBH supply lead. In the event that high battery is removed, the diode allows the device to transition to low battery operation. Functionality During tip open operation, the Tip amplifier is disabled and the Ring amplifier is enabled. The minimum Tip impedance is 30k. The only active path through the device will be the Ring amplifier. In keeping with the MTU characteristics of the device, Ring will not exceed -56.5V when operating from the high battery. Though MTU does not apply to tip open, safety requirements are satisfied. On Hook Power Dissipation The on hook power dissipation of the device during tip open is determined by the operating voltages and quiescent currents and is calculated using Equation 37. P TO = V BH x I BHQ + V BL x I BLQ + V CC x I CCQ (EQ. 37) Low Battery Operation All off hook operating conditions should use the low battery. The prime benefit will be reduced power dissipation. The typical low battery for the device is -24V. However this may be increased to support longer loop lengths or high loop current requirements. Standby conditions may also operate from the low battery if MTU compliance is not required, further reducing standby power dissipation. The quiescent current terms are specified in the electrical tables for each operating mode. Load power dissipation is not a factor since this is an on hook mode. Power Denial Overview The power denial mode (111) will shutdown the entire device except for the logic interface. Loop supervision is not provided. This mode may be used as a sleep mode or to shut down in the presence of a persistent thermal alarm. Switching between high and low battery will have no effect during power denial. High Battery Operation Other than ringing, the high battery should be used for standby conditions which must provide MTU compliance. During standby operation the power consumption is typically 50mW with -100V battery. If ringing requirements do not require full 100V operation, then a lower battery will result in lower standby power. High Voltage Decoupling The 100V rating of the device will require a capacitor of higher voltage rating for decoupling. Suggested decoupling values for all device pins are 0.1F. Standard surface mount ceramic capacitors are rated at 100V. For applications driven at low cost and small size, the decoupling scheme shown below could be implemented. 0.22 0.22 Functionality During power denial, both the Tip and Ring amplifiers are disabled, representing high impedances. The voltages at both outputs are near ground. Thermal Shutdown In the event the safe die temperature is exceeded, the ALM output will go low and DET will go high and the part will automatically shut down. When the device cools, ALM will go high and DET will reflect the loop status. If the thermal fault persists, ALM will go low again and the part will shut down. Programming power denial will permanently shutdown the device and stop the self cooling cycling. VBL VBH HC5518X FIGURE 11. ALTERNATE DECOUPLING SCHEME As with all decoupling schemes, the capacitors should be as close to the device pins as physically possible. 41 HC55180, HC55181, HC55182, HC55183, HC55184 Uncommitted Switch Overview The uncommitted switch is a three terminal device designed for flexibility. The independent logic control input, SWC, allows switch operation regardless of device operating mode. The switch is activated by a logic low. The positive and negative terminals of the device are labeled SW+ and SW- respectively. Test Load The switch may be used to connect test loads across Tip and Ring. The test loads can provide external test termination for the device. Proper connection of the uncommitted switch to Tip and Ring is shown below. TIP Relay Driver The uncommitted switch may be used as a relay driver by connecting SW+ to the relay coil and SW- to ground. The switch is designed to have a maximum on voltage of 0.6V with a load current of 45mA. +5V RELAY RING TEST LOAD SW+ SWSWC FIGURE 13. TEST LOAD SWITCHING SW+ SWSWC FIGURE 12. EXTERNAL RELAY SWITCHING Since the device provides the ringing waveform, the relay functions which may be supported include subscriber disconnect, test access or line interface bypass. An external snubber diode is not required when using the uncommitted switch as a relay driver. The diode in series with the test load blocks current from flowing through the uncommitted switch when the polarity of the Tip and Ring terminals are reversed. In addition to the reverse active state, the polarity of Tip and Ring are reversed for half of the ringing cycle. With independent logic control and the blocking diode, the uncommitted switch may be continuously connected to the Tip and Ring terminals. 42 HC55180, HC55181, HC55182, HC55183, HC55184 Basic Application Circuits CPS1 CPS3 VCC RP1 TIP RP2 CRT RRT RSH RD RIL ILIM CDC VCC CPOL POL CDC E0 F0 F1 F2 DET ALM AGND BGND RTD -IN CFB VFB VBL VBH CRX VRX U1 VRS CRS CTX VTX RS HC55180 RING FIGURE 14. HC55180 BASIC APPLICATION CIRCUIT TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT U1 - Ringing SLIC RRT RSH RIL RS CRX , CRS , CTX , CRT , CPOL , CFB CDC CPS1 CPS2 , CPS3 D1 RP1 , RP2 HC5518x 20k 49.9k 71.5k 210k 0.47F 4.7F 0.1F 0.1F 1N400X type with breakdown > 100V. Protection resistor values are application dependent and will be determined by protection requirements. Standard applications will use 35 per side. VALUE TOLERANCE N/A 1% 1% 1% 1% 20% 20% 20% 20% RATING N/A 0.1W 0.1W 0.1W 0.1W 10V 10V >100V 100V Design Parameters: Ring Trip Threshold = 90mAPEAK , Switch Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device Impedance = 210k/400 = 525, with 39 protection resistors, impedance across Tip and Ring terminals = 603. Where applicable, these component values apply to the Basic Application Circuits for the HC55180, HC55181, HC55182, HC55183 and HC55184. Pins not shown in the Basic Application Circuit are no connect (NC) pins. 43 HC55180, HC55181, HC55182, HC55183, HC55184 CPS1 CPS2 CPS3 VCC RP1 TIP RP2 RING SW+ CRT RRT RSH RD RIL ILIM CDC VCC CPOL POL CDC SWVFB RTD SWC BSEL E0 F0 F1 F2 DET ALM AGND BGND AGND VCC CDC CDC RIL ILIM RRT RSH RD RTD SWC BSEL E0 F0 F1 F2 DET ALM BGND VTX RS -IN CFB CRT D1 VBL VBH CRX VRX U1 RP1 TIP CRS CTX RP2 RING SW+ SWVFB VTX RS -IN CFB VRX U1 CPS1 CPS2 CPS3 VCC D1 VBL VBH CRX HC55181 VRS HC55182 VRS CRS CTX FIGURE 15. HC55181 BASIC APPLICATION CIRCUIT CPS1 CPS2 CPS3 VCC RP1 TIP RP2 CRT -IN RRT RSH RD BSEL RIL ILIM CDC VCC CDC E0 F0 F1 F2 DET ALM AGND BGND RTD VFB CFB RING D1 VBL VBH VRX U1 FIGURE 17. HC55182 BASIC APPLICATION CIRCUIT CPS1 CPS2 CPS3 D1 VCC RP1 TIP RP2 CRT -IN RRT RSH RD BSEL RIL ILIM CDC VCC CPOL POL CDC E0 F0 F1 F2 DET ALM AGND BGND RTD VFB CFB RING VBL VBH VRX U1 CRX CRS CTX CRX CRS CTX HC55183 VRS VTX RS HC55184 VRS VTX RS FIGURE 16. HC55183 BASIC APPLICATION CIRCUIT FIGURE 18. HC55184 BASIC APPLICATION CIRCUIT 44 HC55180, HC55181, HC55182, HC55183, HC55184 Additional Application Diagrams Reducing Overhead Voltages The transmission overhead voltage of the device is internally set to 4V per side. The overhead voltage may be reduced by injecting a negative DC voltage on the receive input using a voltage divider (Fig. 19). Accordingly, the 2-wire port overload level will decrease the same amount as the injected offset. R2 CRX VRX 1:1 HC5518X VBL VD R1 FROM CODEC will not match the 200 teletax impedance. The gain set by RT cancels the impedance matching feedback with respect to the teletax injection point. Therefore the device appears as a low impedance source for teletax. The resistor RT is calculated using the following equation. 200 R T = ------------------------------------------------------------------ x R S 200 + 2 x R P + ( R S 400 ) (EQ. 39) 160 k The signal level across a 200 load will be twice the injected teletax signal level. As the teletax level at VTX will equal the injection level, set RC = RB for cancellation. The value of RB is based on the voice band transhybrid balance requirements. The connection of the teletax source to the transhybrid amplifier should be AC coupled to allow proper biasing of the transhybrid amplifier input TA + CFB VFB RT TELETAX SOURCE -IN FIGURE 19. EXTERNAL OVERHEAD CONTROL The divider shunt resistance is the parallel combination of the internal 160k resistor and the external R2 . The sum of R1 and R2 should be greater than 500k to minimize the additional power dissipation of the divider. The DC gain relationship from the divider voltage, VD, to the Tip and Ring outputs is shown below. V T - R = V BL - 8 - ( 2 x V D ) (EQ. 38) FIGURE 21. TELETAX SIGNALLING With a low battery voltage -24V and a divider voltage of -0.5V, the Tip to Ring voltage is 17V. As a result, the overhead voltage is reduced from 8V to 7V and the overload level will decrease from 3.5VPEAK to 3.0VPEAK. Ringing With DC Offsets The balanced ringing waveform consists of zero DC offset between the Tip and Ring terminals. However, the linear amplifier architecture provides control of the DC offset during ringing. The DC gain is the same as the AC gain, 40V/V per amplifier. Positive DC offsets applied directly to the ringing input will shift both Tip and Ring away from half battery towards ground and battery respectively. A voltage divider on the ringing input may be used to generate the offset (Figure 22). The reference voltage, VREF, can be either the CODEC 2.4V reference voltage or the 5V supply. CODEC Ringing Generation Maximum ringing amplitudes of the device are achieved with signal levels approximately 2.4VP-P. Therefore the low pass receive output of the CODEC may serve as the low level ring generator. The ringing input impedance of 480k minimum should not interfere with CODEC drive capability. A single external capacitor is required to AC coupled the ringing signal from the CODEC. The circuit diagram for CODEC ringing is shown below. 160 k VRX RX OUT 1:1 + 480K HC5518X VRS CODEC + VRS 480K HC5518X VREF VD R1 - - FIGURE 22. EXTERNAL OVERHEAD CONTROL FIGURE 20. CODEC RINGING INTERFACE Implementing Teletax Signalling A resistor, RT, is required at the -IN input of the device for injecting the teletax signal (Figure 20). For most applications the synthesized device impedance (i.e., 600) An offset during ringing of 30V, would require a DC shift of 15V at Tip and 15V at Ring. The DC offset would be created by a +0.375V (VD) at the VRS input. The divider resistors should be selected to minimize the value of the AC coupling capacitor CRS and the loading of the ring generator and voltage reference. The ringing input impedance should also be accounted for in divider resistor calculations. 45 - RS VTX RB RF RC + TX IN +2.4V CODEC R2 CRS FROM RING GEN. HC55180, HC55181, HC55182, HC55183, HC55184 Pin Descriptions PLCC 1 2 3 4 5 6 7 8 9 10 11 SYMBOL TIP BGND VBL VBH SW+ SWSWC F2 F1 F0 E0 TIP power amplifier output. Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Internally separate from AGND but it is recommended that it is connected to the same potential as AGND. Low battery supply connection. High battery supply connection for the most negative battery. Uncommitted switch positive terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. Uncommitted switch negative terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. Switch control input. This TTL compatible input controls the uncommitted switch, with a logic "0" enabling the switch and logic "1" disabling the switch. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. Mode control input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of operation of the device. Mode control input. Mode control input. Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0) comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table shown on page 2). Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode. The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table shown on page 2). Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature (approximately 175oC) and the device has been powered down automatically. Analog ground reference. This pin should be externally connected to BGND. Selects between high and low battery, with a logic "1" selecting the high battery and logic "0" the low battery. This pin is a no connect (NC) on the HC55180. This pin is a no connect (NC) for all the devices. External capacitor on this pin sets the polarity reversal time. This pin is a no connect on the HC55182 and HC55183. Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode. Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC. Transmit output voltage - Output of impedance matching amplifier, AC couples to CODEC. Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching. Impedance matching amplifier summing node. Positive voltage power supply, usually +5V. DC Biasing Filter Capacitor - Connects between this pin and VCC. Ring trip filter network. Loop Current Limit programming resistor. Switch hook detection threshold programming resistor. RING power amplifier output. DESCRIPTION 12 DET 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ALM AGND BSEL NC POL VRS VRX VTX VFB -IN VCC CDC RTD ILIM RD RING All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 46 |
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